Here's my CST from my Thinkpad T60 for you to compare with a MacBookPro1,1 (you'll find that it's really not that different).
Code: Select all
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20091214
*
* Disassembly of ./dsdt.aml, Sat Feb 26 11:43:51 2011
*
*
* Original Table Header:
* Signature "SSDT"
* Length 0x0000065A (1626)
* Revision 0x01
* Checksum 0x0A
* OEM ID "PmRef"
* OEM Table ID "Cpu0Cst"
* OEM Revision 0x00000100 (256)
* Compiler ID "INTL"
* Compiler Version 0x20050513 (537199891)
*/
DefinitionBlock ("./dsdt.aml", "SSDT", 1, "PmRef", "Cpu0Cst", 0x00000100)
{
External (PDC0)
External (CFGD)
External (\C4NA, IntObj)
External (\C3NA, IntObj)
External (\C2NA, IntObj)
External (\_PR_.CPU0, DeviceObj)
External (\_SB_.PCI0.LPC_.EC__.AC__._PSR, IntObj)
Scope (\_PR.CPU0)
{
Name (CMW1, Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
}
})
Name (CMW2, Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x01,
0x01F4
}
})
Name (CMW3, Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x01,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x03, // Access Size
)
},
0x03,
0x11,
0xFA
}
})
Name (CMW4, Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x01,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000030, // Address
0x03, // Access Size
)
},
0x03,
0x39,
0x64
}
})
Name (C1M1, Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
}
})
Name (C1M2, Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001014, // Address
,)
},
0x02,
0x01,
0x01F4
}
})
Name (C1M3, Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001014, // Address
,)
},
0x02,
0x01,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001015, // Address
,)
},
0x03,
0x11,
0xFA
}
})
Name (C1M4, Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001014, // Address
,)
},
0x02,
0x01,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001016, // Address
,)
},
0x03,
0x39,
0x64
}
})
Name (CST1, Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
}
})
Name (CST2, Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001014, // Address
,)
},
0x02,
0x01,
0x01F4
}
})
Name (CST3, Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001014, // Address
,)
},
0x02,
0x01,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001015, // Address
,)
},
0x03,
0x11,
0xFA
}
})
Name (CST4, Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001014, // Address
,)
},
0x02,
0x01,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001016, // Address
,)
},
0x03,
0x39,
0x64
}
})
Method (_CST, 0, NotSerialized)
{
If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
))))
{
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x9D,
0x03E8
}
})
}
If (LAnd (And (CFGD, 0x00200000), And (PDC0, 0x0200)))
{
If (And (CFGD, 0x80))
{
If (\C2NA)
{
Return (CMW1)
}
If (\C3NA)
{
Return (CMW2)
}
If (\_SB.PCI0.LPC.EC.AC._PSR)
{
Return (CMW3)
}
If (\C4NA)
{
Return (CMW3)
}
Return (CMW4)
}
If (LAnd (LNot (And (CFGD, 0x80)), And (CFGD, 0x40
)))
{
If (\C2NA)
{
Return (CMW1)
}
If (\C3NA)
{
Return (CMW2)
}
Return (CMW3)
}
If (And (CFGD, 0x20))
{
If (\C2NA)
{
Return (CMW1)
}
Return (CMW2)
}
Return (CMW1)
}
If (LAnd (And (CFGD, 0x00200000), And (PDC0, 0x0100)))
{
If (And (CFGD, 0x80))
{
If (\C2NA)
{
Return (C1M1)
}
If (\C3NA)
{
Return (C1M2)
}
If (\_SB.PCI0.LPC.EC.AC._PSR)
{
Return (C1M3)
}
If (\C4NA)
{
Return (C1M3)
}
Return (C1M4)
}
If (LAnd (LNot (And (CFGD, 0x80)), And (CFGD, 0x40
)))
{
If (\C2NA)
{
Return (C1M1)
}
If (\C3NA)
{
Return (C1M2)
}
Return (C1M3)
}
If (And (CFGD, 0x20))
{
If (\C2NA)
{
Return (C1M1)
}
Return (C1M2)
}
Return (C1M1)
}
If (And (CFGD, 0x80))
{
If (\C2NA)
{
Return (CST1)
}
If (\C3NA)
{
Return (CST2)
}
If (\_SB.PCI0.LPC.EC.AC._PSR)
{
Return (CST3)
}
If (\C4NA)
{
Return (CST3)
}
Return (CST4)
}
If (LAnd (LNot (And (CFGD, 0x80)), And (CFGD, 0x40
)))
{
If (\C2NA)
{
Return (CST1)
}
If (\C3NA)
{
Return (CST2)
}
Return (CST3)
}
If (And (CFGD, 0x20))
{
If (\C2NA)
{
Return (CST1)
}
Return (CST2)
}
Return (CST1)
}
}
}