Can you please explain what exactly you are doing by patching the CPU0/CPU1 scopes in DSDT in order to enable speedstep feature.
It seems that you are overwriting the _CST function (= what gets executed when the system wants to enter a cstate?) but i couldn't find your code snippet or anything similar neither in the original MacBook1,1 DSDT/SSDTs nor in my Thinkpad x60ts DSDT/SSDTs. There are no _CST functions or C*M* arrays!
All I could find in my TPs SSDT is the following (which is almost similar to what's in the original MacBook1,1 SSDT!):
Code: Select all
Scope (\_PR.CPU0)
{
Name (HI0, 0x00)
Name (HC0, 0x00)
Method (_PDC, 1, NotSerialized)
{
CreateDWordField (Arg0, 0x00, REVS)
CreateDWordField (Arg0, 0x04, SIZE)
Store (SizeOf (Arg0), Local0)
Store (Subtract (Local0, 0x08), Local1)
CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
Name (STS0, Buffer (0x04)
{
0x00, 0x00, 0x00, 0x00
})
Concatenate (STS0, TEMP, Local2)
_OSC (Buffer (0x10)
{
/* 0000 */ 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47,
/* 0008 */ 0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
}, REVS, SIZE, Local2)
}
Method (_OSC, 4, NotSerialized)
{
CreateDWordField (Arg3, 0x00, STS0)
CreateDWordField (Arg3, 0x04, CAP0)
CreateDWordField (Arg0, 0x00, IID0)
CreateDWordField (Arg0, 0x04, IID1)
CreateDWordField (Arg0, 0x08, IID2)
CreateDWordField (Arg0, 0x0C, IID3)
Name (UID0, Buffer (0x10)
{
/* 0000 */ 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47,
/* 0008 */ 0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
})
CreateDWordField (UID0, 0x00, EID0)
CreateDWordField (UID0, 0x04, EID1)
CreateDWordField (UID0, 0x08, EID2)
CreateDWordField (UID0, 0x0C, EID3)
If (LNot (LAnd (LAnd (LEqual (IID0, EID0), LEqual (IID1, EID1)),
LAnd (LEqual (IID2, EID2), LEqual (IID3, EID3)))))
{
Store (0x06, STS0)
Return (Arg3)
}
If (LNotEqual (Arg1, 0x01))
{
Store (0x0A, STS0)
Return (Arg3)
}
Or (And (PDC0, 0x7FFFFFFF), CAP0, PDC0)
If (And (CFGD, 0x01))
{
If (LAnd (LAnd (And (CFGD, 0x01000000), LEqual (And (PDC0,
0x09), 0x09)), LNot (And (SDTL, 0x01))))
{
Or (SDTL, 0x01, SDTL)
OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, 0x01)), DerefOf (Index (SSDT, 0x02
)))
Load (IST0, HI0)
}
}
If (And (CFGD, 0xF0))
{
If (LAnd (LAnd (And (CFGD, 0x01000000), And (PDC0, 0x18
)), LNot (And (SDTL, 0x02))))
{
Or (SDTL, 0x02, SDTL)
OperationRegion (CST0, SystemMemory, DerefOf (Index (SSDT, 0x07)), DerefOf (Index (SSDT, 0x08
)))
Load (CST0, HC0)
}
}
Return (Arg3)
}
}
