600x Ram

[beemer]

Has anyone every tried installing 16 chip 512mb low density ram cards in your 600x?
I know 256mb 16 chip low density cards will work and everyone says the book tells you 256 per slot is the max, but you can get 512mb low density cards for about the same price.
If it works with two cards you could get 1gb.

And yes don't post if you just want to tell me what the book says, I want to hear from someone who has tried it with 512mb 16 chip cards.
Thanks

[Bookworm]

It won't work. The chipset in PCs limits the amount of RAM, and even the chipset's features usualy aren't all used. The 440BX and related chipsets in most turn of the century ThinkPads can handle up to 4 slots, 256Mb each.

No, I haven't actually tried it, but I would have if I didn't already know *why* it can't be done.

Of course, there are ways around the chipset if you know enough about electronics, can solder a notebook motherboard without melting it, (and could stuff that mess back into the case) and know enough about assembly language programming, but if you were that kind of genius, you wouldn't have needed to ask.

[beemer]

Per my original post, has anyone out there actually tried it?
If so what was the result.

No offense, but I can read posts like Bookworms all over the web.

[rkawakami]

Funny, your profile location doesn't say you're from Missouri . All kidding aside, YES, I have just tried installing a Kingston 16 chip 512MB PC133 module in one of my 600X systems (2645-5EU) and as expected, it didn't work. The system powered up, the fan started spinning but no IBM splash screen and no error beeps either. And yes, I verified that the module worked in a T23, and yes I tried both slots in the 600X and yes the 600X is able to boot and recognize two 256MB modules.

Here's WHY it will not work: there is no such thing as a "low density" 512MB module. As far as I know, all standard-sized (i.e. 1.25" high) 512MB modules were built using 8K refresh devices. Sellers who state that they have "low density 512MB" modules don't know what they're talking about. They think that simply having 16 chip modules automatically makes them low density. That's not true. What matters is the memory architecture, specifically, the size of the memory array and directly related to that, the refresh characteristics that were designed into the individual memories being used on the module. If you search around in the archives here for any one of my posts concerning "low density" issues you'll see that this has been discussed many times before. Basically, it can be boiled down to these points (warning: there's some math involved ):

- 16 chip 256MB modules use 16 128Mbit (megabit) devices; 128Mbit can also be thought of as 16MB (megabytes; 8 bits to 1 byte so divide 128 by 8 and you get 16), therefore 16 x 16MB = 256MB
- 16 chip 512MB modules use 16 256Mbit or 32MB devices; 16 x 32MB = 512MB
- the 600X uses the Intel 440BX chipset
- said chipset supports a 15.6uS (microsecond) refresh interval; that is, one refresh signal is generated every 15.6uS by the 440BX
- every 64mS (milliseconds), the entire memory array must be fully refreshed
- 16MB devices have a refresh specification of 4,096 (4K) cycles for every 64mS or dividing 4,096 into 64mS and you get 15.6uS, exactly matching what the 440BX expects and needs
- 32MB devices have a refresh specification of 8,192 (8K) cycles for every 64mS; this is essentially an industry standard that was adopted when the memory manufacturers switched from 16MB (or "low density") designs to 32MB (or "high density")
- that works out to a refresh interval of 7.8uS (64mS/8192), meaning that the chipset has to send out a refresh signal every 7.8uS
- therefore, modules built with 32MB devices will only see half the number of refreshes that they need to operate properly

ref: http://www.intel.com/design/support/faq ... /440bx.htm (FAQ on 440BX; see "Are 256Mbit SDRAM's supported?")
ref: http://download.intel.com/design/chipse ... 063301.pdf (Page 100 of the PDF (4-14, as printed on the page) has details about the memory interface)

[paul*robertson]

Funny, your profile location doesn't say you're from Missouri . All kidding aside, YES, I have just tried installing a Kingston 16 chip 512MB PC133 module in one of my 600X systems (2645-5EU) and as expected, it didn't work. The system powered up, the fan started spinning but no IBM splash screen and no error beeps either. And yes, I verified that the module worked in a T23, and yes I tried both slots in the 600X and yes the 600X is able to boot and recognize two 256MB modules.

Here's WHY it will not work: there is no such thing as a "low density" 512MB module. As far as I know, all standard-sized (i.e. 1.25" high) 512MB modules were built using 8K refresh devices. Sellers who state that they have "low density 512MB" modules don't know what they're talking about. They think that simply having 16 chip modules automatically makes them low density. That's not true. What matters is the memory architecture, specifically, the size of the memory array and directly related to that, the refresh characteristics that were designed into the individual memories being used on the module. If you search around in the archives here for any one of my posts concerning "low density" issues you'll see that this has been discussed many times before. Basically, it can be boiled down to these points (warning: there's some math involved ):

- 16 chip 256MB modules use 16 128Mbit (megabit) devices; 128Mbit can also be thought of as 16MB (megabytes; 8 bits to 1 byte so divide 128 by 8 and you get 16), therefore 16 x 16MB = 256MB
- 16 chip 512MB modules use 16 256Mbit or 32MB devices; 16 x 32MB = 512MB
- the 600X uses the Intel 440BX chipset
- said chipset supports a 15.6uS (microsecond) refresh interval; that is, one refresh signal is generated every 15.6uS by the 440BX
- every 64mS (milliseconds), the entire memory array must be fully refreshed
- 16MB devices have a refresh specification of 4,096 (4K) cycles for every 64mS or dividing 4,096 into 64mS and you get 15.6uS, exactly matching what the 440BX expects and needs
- 32MB devices have a refresh specification of 8,192 (8K) cycles for every 64mS; this is essentially an industry standard that was adopted when the memory manufacturers switched from 16MB (or "low density") designs to 32MB (or "high density")
- that works out to a refresh interval of 7.8uS (64mS/8192), meaning that the chipset has to send out a refresh signal every 7.8uS
- therefore, modules built with 32MB devices will only see half the number of refreshes that they need to operate properly

ref: http://www.intel.com/design/support/faq ... /440bx.htm (FAQ on 440BX; see "Are 256Mbit SDRAM's supported?")
ref: http://download.intel.com/design/chipse ... 063301.pdf (Page 100 of the PDF (4-14, as printed on the page) has details about the memory interface)

Now thats what you call an answer

[beemer]

Thanks Ray!
Your the first one I've found that has tried it.
I didn't know if someone done it and used a BIOS mod to get it to work.
Sometimes people just keep repeating that it can't be done until it becomes law.
I hope this post helps others with the 600x.

Thanks again

[rkawakami]

I doubt that any BIOS update could get around the refresh and/or addressing issues. What might have occurred for those people who claim that a 512MB module works in their system is that the module's Serial Presence Detect (SPD) chip may have been altered. That chip supplies the configuration data of the module to the computer. It essentially tells the computer what size it is, what speeds it supports and so on. While you could probably re-program the SPD data to say that the module needs 15.6uS refreshing, you would be violating the guaranteed specs of the memory devices and thus may encounter some operational failures.

Also, if you read my previous post carefully, you will note that I specifically mentioned "standard-sized" modules. I believe that there were some "double-height" modules used in some Apple computers. It is possible that someone could have managed to put 32 16MB (low density) parts on one module and meet the refresh requirement for the 440BX chipset, but that still leaves the question of whether or not the chipset and/or the motherboard could address it, much less having the room to shoehorn that beast into the belly of the 600X.

edit 3/16/10: Found this while looking around for 512MB modules: http://www.memoryx.net/apl144p512.html It is an Apple 512MB PC133 2" high SODIMM. Looks like 16 devices are on the module so it's probably still "high density" and would not work in a 600X.

[Bookworm]

Are the timing and refresh problems in the hardware (the chipset or the RAM?) or the BIOS? As far as I can tell, desktops that use the 440BX and SDRAM don't have these problems.

Of course, even if a BIOS upgrade did fix the low density problem, you can't create an address line out of thin air. The 440BX only supplies enough for 256Mb per slot.

[rkawakami]

The refresh timing interval of 15.6uS is programmed into the 440BX chipset. If you download the Intel .PDF file I referenced earlier, page 45 of the .PDF (3-19 on the printed page) shows that the fastest that the refresh rate can be set to is 15.6uS. High density parts require that you have a 7.8uS interval available.

Reading further into the .PDF, page 101 shows some of the possible combinations of modules that the chipset can support. Indeed, the slot maximum addressing is 32M x 72 (parity modules; it's x64 for SODIMMs) so that means 256MB per slot.