Coreboot on the X210

[harryK]

Hi,
I updated the coreboot image syncing it with the latest coreboot source, which contains Matthew's patch to enable EPB. I also enabled SATA ALPM and Dev Sleep and a couple of other things for power saving, and included the latest CPU microcode from Intel. BTW note that this version of coreboot sets the TDP to 25W / 44W. It should also be possible to undervolt the processor, but I don't know how

Wow this sounds awesome! Have Matthew's changes been merged into coreboot master? His own Github master latest is 3 months old...

Since I want to build my own version with SeaBIOS & Tinycore Linux as a payload (!), can you give some tips as to what specific power saving things you've enabled and how to do the Intel microcode update? I've done a build of coreboot before but not to this level of customization so might need some guidance here.

Unless they're named differently in Menuconfig, the actual .config file makes no mention of Dev Sleep and ALPM, for example. Where are these options usually configured?

Thanks,
R

Hi,

all these things are in src/mainboard/51nb/x210/devicetree.cb My changes can be seen here: https://github.com/mjg59/coreboot/compa ... 2eae28c511

It's essentially

• SATA ALPM + DevSleep
• PCI CLKREQ (afaik, that stops the pci clocks when idle)
• PCI ASPM L1 substates (except for nvme - for some reason that doesn't work)
• s0ix States - should save power at runtime to those lucky enough to have a screen capable of psr and reaching PC10 (https://01.org/blogs/qwang59/2018/how-a ... ates-linux)

The microcode is downloaded during compilation and added to the image if the option is selected in menuconfig. You could try and build everything pulling my repo https://github.com/harrykipper/coreboot. I synced everything with coreboot master a couple of days ago.

Alternatively, you could clone the coreboot master repository and copy src/mainboard/51nb and src/ec/51nb from Matthew's repo or mine. The .config file is in my repo, or you can pull it from a compiled coreboot image with

Code: Select all

 grep -a CONFIG_ coreboot.rom > .config

[harryK]

Strange. Try booting with intel_iommu=off maybe?
Also, I just realised that I killed the ME with me_cleaner in this release, that could be related to the issue. I'll reupload the image with the full ME in a bit.
FWIW everything works well for me with the deactivated ME, but I don't enable IOMMU and DMAR in my kernel

I'd like to boot with iommu as i use iommu for device pass through and virtualization.
I don't think that ME is related, I think it's one of the changes in the policies.

Hi,

I tried booting with the stock arch kernel. I get some errors (see below), but the nvme drive is fully functional..

Code: Select all

 DMAR: Host address width 39
[    0.225673] DMAR: DRHD base: 0x000000fed90000 flags: 0x0
[    0.225677] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 19e2ff0505e
[    0.225678] DMAR: RMRR base: 0x0000007b800000 end: 0x0000007fffffff
[    0.225680] DMAR-IR: [Firmware Bug]: ioapic 2 has no mapping iommu, interrupt remapping will be disabled
[    0.225683] DMAR-IR: Not enabling interrupt remapping
[    0.225684] DMAR-IR: Failed to enable irq remapping. You are vulnerable to irq-injection attacks.
[    0.226890] x2apic: IRQ remapping doesn't support X2APIC mode

[verynice]

I'd like to boot with iommu as i use iommu for device pass through and virtualization.
I don't think that ME is related, I think it's one of the changes in the policies.

Hi,

I tried booting with the stock arch kernel. I get some errors (see below), but the nvme drive is fully functional..

Code: Select all

 DMAR: Host address width 39
[    0.225673] DMAR: DRHD base: 0x000000fed90000 flags: 0x0
[    0.225677] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 19e2ff0505e
[    0.225678] DMAR: RMRR base: 0x0000007b800000 end: 0x0000007fffffff
[    0.225680] DMAR-IR: [Firmware Bug]: ioapic 2 has no mapping iommu, interrupt remapping will be disabled
[    0.225683] DMAR-IR: Not enabling interrupt remapping
[    0.225684] DMAR-IR: Failed to enable irq remapping. You are vulnerable to irq-injection attacks.
[    0.226890] x2apic: IRQ remapping doesn't support X2APIC mode

Hi,
I'm using Samsung 970 pro nvme drive and a custom kernel based around iommu.
I'll try to flash me back and will report back as soon as I can.
I can boot with intel_iommu=off, but only half of the times. (and it has the same
dmesg messages)
With the old build I had 4W idle in powertop
Now I have ~3.33W idle
I'll try to build coreboot later as I want to get libgfxinit working, but
I have gentoo with clang and musl without gcc and binutils, don't
know if it's possible to bootstrap from this.

[verynice]

Aaaand this is not ME problem.
I flashed only me region firstly, it had the same problems.
Then I flashed the previous build and it worked. I tried to flash
only bios region and it still has the same problem.

[mjg59]

Hi,

all these things are in src/mainboard/51nb/x210/devicetree.cb My changes can be seen here: https://github.com/mjg59/coreboot/compa ... 2eae28c511

Thanks, I'll merge these in!

[mjg59]

Hi,

all these things are in src/mainboard/51nb/x210/devicetree.cb My changes can be seen here: https://github.com/mjg59/coreboot/compa ... 2eae28c511

Thanks, I'll merge these in!

Ok, merged these with the following exceptions:

1) I've left the wake on LAN flag set - this just controls whether the chipset will respond to WoL, it doesn't actually power up the ethernet controller unless the user explicitly enables that, so it should have a minimal impact on power consumption during suspend.
2) I left DPTF disabled - it doesn't do anything without EC cooperation, and the EC doesn't have support for it.
3) I left s0ix states disabled - they won't be used unless declared in the FADT, and doing that disables normal S3 sleep. Linux doesn't have good support for that yet.

Thanks!

[harryK]

Thanks, I'll merge these in!

Ok, merged these with the following exceptions:

1) I've left the wake on LAN flag set - this just controls whether the chipset will respond to WoL, it doesn't actually power up the ethernet controller unless the user explicitly enables that, so it should have a minimal impact on power consumption during suspend.
2) I left DPTF disabled - it doesn't do anything without EC cooperation, and the EC doesn't have support for it.
3) I left s0ix states disabled - they won't be used unless declared in the FADT, and doing that disables normal S3 sleep. Linux doesn't have good support for that yet.

Thanks!

Great. Thanks a lot! One question: why do you enable hotplug for the wireless card root port? And not, say, for the NVMe port as well? Or for no port at all, since these cards are not meant to be hotplugged anyway?

[verynice]

Ok, merged these with the following exceptions:

1) I've left the wake on LAN flag set - this just controls whether the chipset will respond to WoL, it doesn't actually power up the ethernet controller unless the user explicitly enables that, so it should have a minimal impact on power consumption during suspend.
2) I left DPTF disabled - it doesn't do anything without EC cooperation, and the EC doesn't have support for it.
3) I left s0ix states disabled - they won't be used unless declared in the FADT, and doing that disables normal S3 sleep. Linux doesn't have good support for that yet.

Thanks!

Great. Thanks a lot! One question: why do you enable hotplug for the wireless card root port? And not, say, for the NVMe port as well? Or for no port at all, since these cards are not meant to be hotplugged anyway?

Hi, can you be of help and compile the latest build from mjg59's branch?
I want to test whether iommu will be working or not.
If not I'll try to find the culprit. And will report later.

[harryK]

Great. Thanks a lot! One question: why do you enable hotplug for the wireless card root port? And not, say, for the NVMe port as well? Or for no port at all, since these cards are not meant to be hotplugged anyway?

Hi, can you be of help and compile the latest build from mjg59's branch?
I want to test whether iommu will be working or not.
If not I'll try to find the culprit. And will report later.

Go on, I just uploaded it. Could it be due to the cpu microcode? Were you applying it before?

[verynice]

Hi, can you be of help and compile the latest build from mjg59's branch?
I want to test whether iommu will be working or not.
If not I'll try to find the culprit. And will report later.

Go on, I just uploaded it. Could it be due to the cpu microcode? Were you applying it before?

Don't know about the microcode. But I have never applied it before, yes.
Still, new build has the same iommu error.

[mjg59]

Great. Thanks a lot! One question: why do you enable hotplug for the wireless card root port? And not, say, for the NVMe port as well? Or for no port at all, since these cards are not meant to be hotplugged anyway?

Oh ha good catch. The connector on my board is slightly bad - I need to physically poke the card after boot in order to trigger a hotplug event and get it to show up. I should really just pull the board out and resolder that.

[harryK]

Go on, I just uploaded it. Could it be due to the cpu microcode? Were you applying it before?

Don't know about the microcode. But I have never applied it before, yes.
Still, new build has the same iommu error.

You could try and apply the microcode update while using the stock bios or the last working coreboot image and see if that's what's causing the error.

[verynice]

Don't know about the microcode. But I have never applied it before, yes.
Still, new build has the same iommu error.

You could try and apply the microcode update while using the stock bios or the last working coreboot image and see if that's what's causing the error.

And it's not microcode.
So it's one of the changes.

[harryK]

libgfxinit has been finally enabled for kabylake+ in upstream coreboot. Just made a build for the X210, if you want to give it a go. https://github.com/harrykipper/x210/blo ... fxinit.rom

If you want to compile your own head here: https://github.com/harrykipper/coreboot and select libgfxinit in menuconfig under Devices. With libgfxinit you don't need to include vgabios or vbt in the final image any more (although linux complains that it can't find vbt), you can safely unselect them in menuconfig. Everything seems to work.

[flyingfishfinger]

Oh, interesting.

Is the advantage here solely that the VGA blobs don't need to be included anymore and thus we save ROM space?

Also, unrelated question: Has anyone tried building u-boot as a payload for this yet?

R

[flyingfishfinger]

Hi,
After playing with this for a week or so, a few questions arose:

- Still unable to boot an existing Windows install with Tianocore. Some Googling suggests setting the SATA mode to IDE may help (the error is "INACCESSIBLE BOOT VOLUME" or "BOOT VOLUME NOT FOUND" or similar). Does this port have a KConfig option for changing this setting?

- It takes quite a while to reach any splash screen (SeaBIOS, Tianocore) whether or not the ME is sanitized. Not a big issue, but why might this be?

- I tried replacing the boot logo for Tianocore, but apparently I"m not having any luck matching the exact right format. Any pointers?

- Is there a way I can boot both legacy and UEFI images?

I haven't gotten DUET to work as a SeaBIOS payload (the image from the 2018 release seems to load correctly with some debug output but it immediately boot loops - I've read of a 4GB RAM restriction but I'm not a developer so I can't do anything about that). The Coreboot build of Tianocore doesn't support CSM modules, so I can't do it the other way around either.

- After I sleep / suspend, the mouse doesn't work anymore until I reboot. Feature or bug?

- Building with libgfxinit fails with an error related to Read_EDID or something like that. I can pull the exact error message if that's helpful

- The SD card reader does, indeed, NOT work.

Cheers,
Rafael

[harryK]

Hi,
After playing with this for a week or so, a few questions arose:

- Still unable to boot an existing Windows install with Tianocore. Some Googling suggests setting the SATA mode to IDE may help (the error is "INACCESSIBLE BOOT VOLUME" or "BOOT VOLUME NOT FOUND" or similar). Does this port have a KConfig option for changing this setting?

- It takes quite a while to reach any splash screen (SeaBIOS, Tianocore) whether or not the ME is sanitized. Not a big issue, but why might this be?

I don't know what it could be, but I had this when I was using the me.bin provided by mjg59. When I extracted it from the stock rom on my machine the boot times became normal. The settings related to the ME in the stock bios prior to extracting it might play a role.
Also make sure that SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set.

- I tried replacing the boot logo for Tianocore, but apparently I"m not having any luck matching the exact right format. Any pointers?

You need to create an 8 bit indexed .bmp with a resolution much smaller than that of the screen. GIMP doesn't produce a valid file, this tool works well -> https://online-converting.com/image/convert2bmp/

- After I sleep / suspend, the mouse doesn't work anymore until I reboot. Feature or bug?

If you mean an external mouse, that's an EC bug (see vladisslav2011's post). It also happens very occasionally that the trackpoint/touchpad don't work after suspend, but that also points to the EC, as it happened with the stock bios too.

[flyingfishfinger]

Hi,
Thanks for the comments, I'll try out the image thing.

Any further thoughts on either the SATA question or the SD issue?

I do a decent amount of photography so having a non-functional SD card is almost a dealbreaker

Cheers,
R

[verynice]

I'm trying to get libgfxinit working on a NV126A1M-N52 (2880x1920)
There are some problems though:
1. Internal screen has only backlight on and works only when one plugs external display
2. resolution in the console (drm) is used from the external display.

I was thinking that there is some kind of ordering problem.
How can one fix that?

[harryK]

I'm trying to get libgfxinit working on a NV126A1M-N52 (2880x1920)
There are some problems though:
1. Internal screen has only backlight on and works only when one plugs external display
2. resolution in the console (drm) is used from the external display.

I was thinking that there is some kind of ordering problem.
How can one fix that?

Try changing the order of ports in src/mainboard/51nb/x210/gma-mainboard.ads putting Internal at the top. Also, check the timings of your screen by running intel_vbt_decode --file=/sys/kernel/debug/dri/0/i915_vbt | grep Power. The values in Power Sequence have to be entered at the top of src/mainboard/51nb/x210/mainboard.cb

[verynice]

In order to get the libgfxinit semi-working with N52 one needs:
http://dpaste.com/3JFBQ6B.txt
but something sets: Dotclock => 353900000

Also there is datasheet with t* https://z3d9b7u8.stackpathcdn.com/pdf-d ... 52-BOE.pdf

[flyingfishfinger]

Is the ACPI implementation in these builds "complete"? I have not had any success booting any Windows installs or installers (have tried Windows 7 and 10, SeaBIOS & Tianocore, USB2 and USB3 drives in various combinations). I've read some stuff that Windows requires a strict ACPI implementation, so I'm wondering if that may not be the case with these builds.

Matt & Harry (or anyone else), have you ever tried & succeeded in booting Windows with this?

Cheers,
R

[verynice]

Is the ACPI implementation in these builds "complete"? I have not had any success booting any Windows installs or installers (have tried Windows 7 and 10, SeaBIOS & Tianocore, USB2 and USB3 drives in various combinations). I've read some stuff that Windows requires a strict ACPI implementation, so I'm wondering if that may not be the case with these builds.

Matt & Harry (or anyone else), have you ever tried & succeeded in booting Windows with this?

Cheers,
R

I installed Windows 10 yesterday with no problems whatsoever (with libgfxinit and tianocore).
There are problems after the install (minor ones and they depend on EC afaik)
Those are:
1. NumLock is on after boot
2. CapsLock too
3. some weirdness in trackpoint behaviour (maybe it's working properly))

[harryK]

I installed Windows 10 yesterday with no problems whatsoever (with libgfxinit and tianocore).

What storage type? The Windows installer never detected my nvme drive.

[verynice]

I installed Windows 10 yesterday with no problems whatsoever (with libgfxinit and tianocore).

What storage type? The Windows installer never detected my nvme drive.

samsung 970 pro nvme

[flyingfishfinger]

Tried re-building with Tianocore. Finding an interesting problem that I didn't have before:

I get no splash screen nor boot menu, but if I hit "Enter" Ubuntu boots correctly (it must be the first menu entry) and the first thing I see is "Ubuntu 19.10" with the loading dots.

Building with vga blobs (not libgfxinit) and X64 Tianocore Stable Release Build.

I've deleted and re-pulled both of Harry's repos (coreboot and X210) but I can't figure out why I don't get the rabbit anymore...

R

[verynice]

Tried re-building with Tianocore. Finding an interesting problem that I didn't have before:

I get no splash screen nor boot menu, but if I hit "Enter" Ubuntu boots correctly (it must be the first menu entry) and the first thing I see is "Ubuntu 19.10" with the loading dots.

Building with vga blobs (not libgfxinit) and X64 Tianocore Stable Release Build.

I've deleted and re-pulled both of Harry's repos (coreboot and X210) but I can't figure out why I don't get the rabbit anymore...

R

>I get no splash screen nor boot menu, but if I hit "Enter" Ubuntu boots correctly (it must be the first menu entry) and the first thing I see is "Ubuntu 19.10" with the loading dots.
You've got the 2880x1920 screen? If so, you need the patch that I've added before.
Also, you can be of help, now my laptopp is semi-bricked and I have no programmer, if you have time you can try cooperating with nico_h(icon) and fix the libgfxinit he asked me to check the vbt from stock bios (and i can't do this now) and to contact the i915 devs.

[flyingfishfinger]

Hah yeah that's why the first thing I did was install this guy. Now I can brick all I want, I just swap the chip after boot.

Can you PM me with the details? Happy to collaborate but keep in mind I'm not a software engineer, so the best thing I can do is change the code specifically where people tell me to and build / configure things. If that's good enough, great!

Cheers,
R

[flyingfishfinger]

I fixed the SD card and fingerprint reader, if anyone needs that.

Add this to src/mainboard/51nb/x21/devicetree.cb:

register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # FPR?
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # SD?

Enjoy,
R

[verynice]

I fixed the SD card and fingerprint reader, if anyone needs that.

Add this to src/mainboard/51nb/x21/devicetree.cb:

register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # FPR?
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # SD?

Enjoy,
R

Can you post this here? https://review.coreboot.org/c/coreboot/+/32531/